The dynamic power consumed by a device is a function of the square of its power supply voltage. In order to save power, it is desirable for the supply voltage to be low.
Static memories are very sensitive to the power supply voltage, a slight variation being able to cause errors or even to cause the entire system fail. Moreover, too low a power supply voltage leads to information loss when the power supply voltage is below the minimum memory retention voltage value.
Thus within complex systems of the “System on Chip”-type consisting of SRAM embedded memory, it is a question of making sure that the performance as regards dynamic consumption reduction are not limited by the SRAM memory or memories.
Furthermore, in memory cell array devices, the column structure requires that the power supply voltage (VDDM) for a column is the same for all the cells in the column. This structure also requires a “weak link” principle, that is to say that the properties of the most restricting cell have an impact on the whole column containing it, in particular by its minimum retention voltage.
Moreover, memory cell allows to carry out either read operation or write operation to which operation margins are associated. These margins are called respectively “Static Noise Margin” and “Write Margin” in Anglo-Saxon material. These margins are antagonistic.
Thus, the lower the power supply voltage is, the lower the operation margin is. More exactly, it is the dispersion in the margin value which is detrimental. In fact, the margins are relatively insensitive to variations in the power supply voltage but ever higher dispersions lead to ever more limited variation problems in the power supply voltage.
The present invention comes under the framework of devices providing the means for carrying out low-voltage write operations, that is to say, for a given technology, lower than the rated voltage. For example, for a rated voltage of 1.2V, performing write operations at 0.7V.
All systems are currently aiming at a reduction in memory sizes. However a reduction in the size of the components increases their dispersion. Indeed, there is high electrical variability in the transistors which have an impact on a memory cell's reading and writing margins.
A memory cell's power supply depends in particular on the “PVT” (Process Voltage Temperature) conditions for the system (circuit) incorporating it, that is to say the technological process, voltage and temperature conditions.
Because of these constraints (PVT, operation margins, local mismatches or separation), a cell's power supply voltage VDDM has to be varied in order to promote reading or writing. Typically, a reduction in the power supply voltage promotes write operations and conversely an increase in the power supply voltage favours a memory cell's read operations.
The present invention comes under the framework of devices intended to favour the write margin, reading being operational over a wide range of voltages.
Such a device is known to those skilled in the art, in particular through the example given in the document U.S. Pat. No. 6,954,396 for state of the prior art.
This document describes a device comprising means for under-volting the power supply voltage VDDM for the cells so as to promote write operations, and means for over-volting the power supply voltage VDDM for the cells so as to promote read operations. These means allows to establish static polarisations for the read and write phases.
The means required for over-volting are costly in power and run counter to the reduction in dynamic consumption desired.